Design and implementation of a forward two-PLL Diophantine Frequency Synthesizer with 500× resolution improvement

The design, implementation and measurements of a forward two-PLL diophantine frequency synthesizer are presented. This case study illustrates how the diophantine frequency synthesis (DFS) methodology, introduced at the IEEE frequency control symposium of 2006, is used to design a two-PLL synthesizer with frequency resolution 500 times finer than that of the two constituent PLLs while maintaining the PLLspsila phase-comparator frequencies, loop-bandwidths, frequency ranges and spectral purity. The Diophantine frequency synthesizer is driven by a 30 MHz input reference and provides an output frequency range of 0 - 30 MHz with 60 Hz resolution when the output-frequency resolutions of the two constituent PLLs are 29 kHz and 31 kHz.