DocumentCode
2817479
Title
Investigation of 6T SOI SRAM Cell Stability Including Quantum and Gate Direct Tunneling Effects by Three-dimensional Device Simulation
Author
Tanabe, R. ; Tosaka, Y. ; Ashizawa, Y. ; Oka, H.
Author_Institution
Fujitsu Laboratories Ltd. Fuchigami 50, Akiruno, Tokyo, 197-0833 Japan. E-mail: tanabe.ryou@jp.fujitsu.com
fYear
2005
fDate
01-03 Sept. 2005
Firstpage
43
Lastpage
46
Abstract
This paper shows the impacts of the tunneling leakage current and quantum effect on Static Noise Margin (SNM) and soft error phenomenon for 6T type SOI SRAM by direct 3D process and devise simulations. Below 1.0 nm gate oxide thickness, the influence on SRAM SNM cannot be negligible. Soft error calculations for SOI SRAM cell show SOI devices are very strong for α-particle injections, but for heavy-ion injections, soft error might occur easily and both quantum and tunneling leakage current effects should be considered for accurate future scaled SRAM cell simulation.
Keywords
CMOS technology; Circuit simulation; Leakage current; MOS devices; Poisson equations; Random access memory; Stability; Tunneling; Voltage; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on
Print_ISBN
4-9902762-0-5
Type
conf
DOI
10.1109/SISPAD.2005.201468
Filename
1562020
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