DocumentCode
2817817
Title
Three and four-dimensional parity-check codes for correction and detection of multiple errors
Author
Anne, Naveen Babu ; Thirunavukkarasu, Utthaman ; Latifi, Shahram
Author_Institution
Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA
Volume
2
fYear
2004
fDate
5-7 April 2004
Firstpage
837
Abstract
We examine two different schemes of three dimensional parity checking codes that can be obtained by arranging the information and parity bits as a combination of rows and columns or by arranging them as two dimensional planes to obtain a three dimensional cube. Finding the number of errors detected and the numbers of errors corrected has been the main aim of this work. The code rate and the overhead of each scheme has been calculated and compared with that of the standard parity schemes available. Some general equations have been derived to represent these families of codes. A four dimensional scheme that can detect and correct more multiple errors has also been discussed.
Keywords
error correction codes; error detection codes; parity check codes; error correction; error detection; four-dimensional parity-check code; information bit; parity bit; three dimensional parity checking code; Code standards; Computer errors; Equations; Error correction; Error correction codes; Information technology; Parity check codes; Redundancy; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on
Print_ISBN
0-7695-2108-8
Type
conf
DOI
10.1109/ITCC.2004.1286763
Filename
1286763
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