Coupled Simulation of Device Performance and Heating of Vertically Stacked Three-Dimensional Integrated Circuits

We have developed a method for calculating the temperature distribution of a three-dimensional (3D) integrated circuit (IC) and the performance of a single device self-consistently. At the device level, we resolve effects of channel temperatures and thermal boundary conditions on device performance. Thus we obtain non-isothermal device characteristics for a representative device of the technology node used to fabricate the 3D-IC. At the 3D-IC level, we first approximate the average heat generation of each device on the chip using a statistical Monte Carlo method. We second determine effects of the chip layout and the fabrication materials on thermal coupling. Next we calculate thermal profile of the 3D-IC in conjunction with the individual device operations, 3D-IC layout and full-chip workload statistics. Our technique offers a numerical method to isolate affects of chip layout, floor-plan and operational activity on 3D-IC thermal profile. Thus it enables designers to pinpoint potential hotspots, and test new design paradigms for cooling methods.