A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter- and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the distribution of circuit performance. In order to verify our model, test chips which consist of transistors and ring oscillators were fabricated using a 130nm CMOS technology. Simulated delay/skew variations of ring oscillators agree well with the measurement of test chips, maintaining a reasonable accuracy of 85 %. Especially, we show that as the distance of the two ring oscillators becomes larger, the timing skew between them becomes bigger. Moreover, the sensitivity analysis for the performance of simple analog and digital circuit, is performed in terms of inter-and intra-die variation.