Title :
The design of multiplierless digital data transmission filters with powers-of-two coefficients
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA
Abstract :
An efficient search technique is presented for the design of FIR (finite impulse response) digital transmit and receive matched filters whose coefficients are represented by sums and/or differences of powers-of-two. These filters are ideally suited for custom VLSI implementation since power-of-two multipliers are obtained for free in a dedicated hardware implementation. Thus only a few adders or subtracters are required for each tap of the filter, and therefore fairly high-order filters can be implemented on a single VLSI chip. Due to their very simple structure these multiplierless filters could potentially operate at very high sampling rates to accommodate baud rates in the microwave digital radio range
Keywords :
VLSI; data communication equipment; digital filters; matched filters; radiofrequency filters; FIR filter; VLSI chip; adders; baud rates; custom VLSI; digital receive filter; digital transmit filter; filter coefficients; high-order filters; matched filters; microwave digital radio; multiplierless digital data transmission filters; power-of-two multipliers; powers-of-two coefficients; sampling rates; search technique; subtracters; Adders; Data communication; Digital communication; Digital filters; Finite impulse response filter; Hardware; Matched filters; Microwave filters; Sampling methods; Very large scale integration;
Conference_Titel :
Telecommunications Symposium, 1990. ITS '90 Symposium Record., SBT/IEEE International
Conference_Location :
Rio de Janeiro
DOI :
10.1109/ITS.1990.175640