ESL flows are enabled by high-level synthesis with universality

Due to their size and complexity, SoCs today require a “whole-system” approach to validation and verification, using real data traffic, throughout the design cycle. Instead of isolated IP verification with custom testbenches, followed by system integration, designers need to start with whole-system models in which subsystems can be independently substituted by refined models and IP blocks, so that there is a continuous system-level validation. Design languages need to be universal to express configurations that are so heterogeneous, both in the functionality and in level of abstraction. Further, they need to be universally synthesizable so that any such configuration can be run on hardware-assisted verification platforms (such as FPGAs) to achieve the speeds needed for meaningful validation and verification.