• DocumentCode
    2819029
  • Title

    Utility of transaction-level hardware models in refinement checking

  • Author

    Mahajan, Yogesh ; Malik, Sharad

  • Author_Institution
    Dept. of EE, Princeton Univ., Princeton, NJ, USA
  • fYear
    2010
  • fDate
    10-12 June 2010
  • Firstpage
    121
  • Lastpage
    128
  • Abstract
    Verifying a cycle-accurate RTL model against its functional specification using refinement checking uses a joint execution model to compare the executions of the two models. Creating and instrumenting such a joint execution model manually can be tedious and error-prone. In this paper, we illustrate the use of transaction-based models (e.g.) in simplifying the process of creating and instrumenting joint execution models for refinement checking. We first show how transaction-based specification and implementation models allow simple refinement relations to be written using model variables and constructs. We then show how a joint encoding of the two models can be generated together with assertions expressing the specified refinement relation. This approach avoids the manual bookkeeping otherwise needed for coordinating the executions of the design and the specification, and exchanging information between the two models. We illustrate the ideas on a toy example.
  • Keywords
    formal specification; formal verification; logic circuits; transaction processing; functional specification; joint execution model; refinement checking; transaction-level hardware models; Concurrent computing; Context modeling; Design methodology; Encoding; Hardware; History; Instruction sets; Instruments; Logic; Microarchitecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International
  • Conference_Location
    Anaheim, FL
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4244-7805-7
  • Type

    conf

  • DOI
    10.1109/HLDVT.2010.5496650
  • Filename
    5496650