A dual-processors multithreaded architecture and its driven execution model

Author

Xiao, Liquan ; Xu, Weixia ; Zhou, Xingming

Author_Institution

Dept. of Comput., Changsha Inst. of Technol., China

fYear

1997

fDate

19-21 Mar 1997

Firstpage

214

Lastpage

219

Abstract

The software overhead which includes interprocess communication latency and the overhead of management processes or threads, is a crucial factor to affect the performance of massively parallel processors system. Multiple threaded architecture can effectively reduce and hide the software overhead. Many models need to be implemented inside a microprocessor. Conversely, this paper addresses a multiple threaded architecture adopted for current microprocessors and implements the architecture using hardware description language. Furthermore, the paper presents its driven execution model and evaluates the performance of the presented multithreading system using a trace driven simulator

Keywords

discrete event simulation; parallel architectures; performance evaluation; driven execution model; dual-processors multithreaded architecture; hardware description language; interprocess communication latency; management processes; massively parallel processors; microprocessors; multiple threaded architecture; performance; software overhead; trace driven simulator; Communication switching; Computer architecture; Costs; Delay; Memory management; Microprocessors; Multiprocessor interconnection networks; Multithreading; Operating systems; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Parallel and Distributed Computing, 1997. Proceedings

Conference_Location

Shanghai

Print_ISBN

0-8186-7876-3

Type

conf

DOI

10.1109/APDC.1997.574035

Filename

574035