DocumentCode :
2819535
Title :
Thermo-mechanical stress characterization of tungsten-fill through-silicon-via
Author :
Dao, Thuy ; Triyoso, Dina H. ; Mora, Rode ; Kropewnicki, Tom ; Griesbach, Brian ; Booker, Doug ; Petras, Mike ; Adams, Vance
Author_Institution :
Freescale Semicond., Austin, TX, USA
fYear :
2010
fDate :
26-29 April 2010
Firstpage :
7
Lastpage :
10
Abstract :
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30 μm length the stress is 45% greater compared to the case of 7 μm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.
Keywords :
integrated circuit layout; stress analysis; three-dimensional integrated circuits; tungsten; 2D integrated circuit layout; 3D TSV stress simulations; 3D structure profile; Flexus bowing measurement; TSV design; W; Wright etch method; longitudinal side walls; pressure 200 MPa; size 30 mum; size 7 mum; tensile stress; thermo-mechanical stress characterization; transverse axis; tungsten-fill through-silicon-via; Integrated circuit layout; Semiconductor films; Shape; Silicon; Stress measurement; Tensile stress; Thermal stresses; Thermomechanical processes; Through-silicon vias; Tungsten;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
Type :
conf
DOI :
10.1109/VDAT.2010.5496677
Filename :
5496677
Link To Document :
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