Title :
3D integration technology for energy efficient system design
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
CMOS scaling will continue, doubling transistor integration capacity every two years, providing billions of transistors to enable future novel systems. 3D integration technology will open the doors even further, changing the landscape and allowing integration of diverse functionality to realize energy-efficient and affordable complex systems that will continue to deliver higher performance. This paper presents how to exploit this new technology for energy efficient system design.
Keywords :
CMOS integrated circuits; large-scale systems; 3D integration technology; CMOS scaling; complex systems; doubling transistor integration capacity; energy efficient system design; CMOS technology; Cost function; Energy efficiency; Frequency; Logic design; Moore´s Law; Random access memory; System-on-a-chip; Through-silicon vias; Voltage;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496678
