• DocumentCode
    2819631
  • Title

    Real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator for a multi-media SoC

  • Author

    Higuchi, Ryohei ; Teraoka, Eiichi ; Higashida, Motoki

  • Author_Institution
    Renesas Technol. Corp., Itami, Japan
  • fYear
    2010
  • fDate
    26-29 April 2010
  • Firstpage
    21
  • Lastpage
    24
  • Abstract
    Latest multi-media SoCs used in a digital product such as digital TV have a structure where a number of IPs with real-time requirement share one channel of off-chip SDRAM using high-frequency bus to achieve multi-function, high-performance, and low-cost. Thus, such a bus system is required that satisfies real-time requirement, realizes high-efficiency, and has hierarchical structure. In this bus system, bus arbitration plays a crucial role. In this paper, we show Static arbitration has an advantage in bus efficiency over existing arbitration algorithms. And we propose a real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator and the Priority Level Transmission Mechanism. Simulation results show that the proposed bus system can satisfy real-time requirement, and is practical and efficient.
  • Keywords
    DRAM chips; system-on-chip; IP; bus efficiency; high-frequency bus; multi-media SoC; off-chip SDRAM; priority level transmission mechanism; real-time hierarchical bus system; static arbitration; timer-controlled priority allocator; Consumer products; Delay; Digital TV; Frequency conversion; Multimedia communication; Multimedia systems; Real time systems; SDRAM; Terminology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
  • Conference_Location
    Hsin Chu
  • Print_ISBN
    978-1-4244-5269-9
  • Electronic_ISBN
    978-1-4244-5271-2
  • Type

    conf

  • DOI
    10.1109/VDAT.2010.5496682
  • Filename
    5496682