Title :
A wide-range all-digital delay-locked loop in 65nm CMOS technology
Author :
Chung, Ching-Che ; Chang, Chia-Lin
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Abstract :
An ultra wide-range delay-locked loop (DLL) has been fabricated in 65nm CMOS technology. The proposed leakage delay unit (LDU) can easily generate a large propagation delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is 1.8mW @1GHz with very small active area (0.01mm2).
Keywords :
CMOS digital integrated circuits; delay lock loops; integrated circuit design; CMOS technology; DLL circuit; cycle-controlled delay unit; frequency 500 kHz to 1 GHz; high-speed digital counter; leakage delay unit; power 1.8 mW; propagation delay; size 65 nm; very low-frequency operation; wide-range all-digital delay-locked loop; CMOS process; CMOS technology; Charge pumps; Circuits; Delay lines; Digital control; Energy consumption; Leakage current; Propagation delay; System-on-a-chip; All digital delay-locked loop (ADDLL); cycle-controlled delay unit; digital controlled delay line; wide-range operation;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496693
