A nonlinear PRNG using digitized logistic map with self-reseeding method

Author

Li, Chung-Yi ; Chang, Tsin-Yuan ; Huang, Chien-Chih

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2010

fDate

26-29 April 2010

Firstpage

108

Lastpage

111

Abstract

This paper proposes a self-reseeding pseudo RNG (PRNG) based on digitized logistic map to introduce small perturbations periodically so that the low-period can be removed and the randomness can be enhanced. The strategy and the optimization of selecting reseeding period with corresponding fixed pattern are demonstrated. The resultant PRNG generates random sequence fulfilling all the randomness requirements in proportion of NIST SP 800-22 test suite, and the average period can be more than 65 folds. Furthermore, the proposed PRNG is validated by a hardware implementation using TSMC 0.18 μm CMOS process with throughput faster than 250 Mbit/s.

Keywords

CMOS logic circuits; logic design; random number generation; CMOS process; NIST SP 800-22 test suite; digitized logistic map; nonlinear PRNG; pseudo random number generator; random sequence; self reseeding method; size 0.18 nm; CMOS process; Chaos; Costs; Hardware; Logistics; Mathematics; NIST; Random sequences; Testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Conference_Location

Hsin Chu

Print_ISBN

978-1-4244-5269-9

Electronic_ISBN

978-1-4244-5271-2

Type

conf

DOI

10.1109/VDAT.2010.5496703

Filename

5496703