Title :
High speed phase detector design
Author :
Jia, Cheng ; Choi, Munkang ; Milor, Linda ; Ho, Sheng-Feng ; Huang, Hong-Yi
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Two phase detector (PD) designs for phase-locked loops (PLLs) and delay-locked loops (DLLs) are proposed in this paper. The first one is a high speed dynamic PD and the second one is a combined PD and charge pump (CP) circuit. The two PDs are designed with 0.18 μm TSMC process parameters and have been simulated using HSPICE.
Keywords :
delay lock loops; integrated circuit design; phase detectors; phase locked loops; 0.18 micron; HSPICE; TSMC process; charge pump circuit; delay-locked loops; phase detector; phase-locked loops; Charge pumps; Circuits; Delay; Detectors; Feedback; Frequency; Jitter; Phase detection; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562256
