• DocumentCode
    2820129
  • Title

    Conditional threshold wear-leveling algorithm for multi-channel NAND flash memory

  • Author

    Hsieh, Wen-Kai ; Ma, Hsi-Pin

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    26-29 April 2010
  • Firstpage
    147
  • Lastpage
    150
  • Abstract
    Recently, NAND flash memory has become a widely-used data storage media. However, it has endurance problem that each NAND flash block has limited erase cycles. The first time erase failure usually occurs when a block has over 10K-100K erase cycles. Wear-leveling is a technique to solve this problem and extend the lifetime of a flash memory. In this paper, a conditional threshold wear-leveling algorithm fitting multi-channel architecture is proposed. The overall wear-leveling operation is separated and distributed to different channels. This reduces the runtime of the wear-leveling operation. The conditional threshold can reduce extra erase operations caused by wear-leveling when the flash memory is young. As the flash memory becomes older, the smaller threshold makes wear-leveling work more frequently to get more even erase cycle distribution.
  • Keywords
    NAND circuits; flash memories; conditional threshold; erase cycles; multi channel NAND flash memory; temperature 10 K to 100 K; wear-leveling algorithm; wear-leveling operation; Ear; Electric shock; Embedded system; Energy consumption; Flash memory; Hard disks; Magnetic devices; Runtime; Solid state circuits; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
  • Conference_Location
    Hsin Chu
  • Print_ISBN
    978-1-4244-5269-9
  • Electronic_ISBN
    978-1-4244-5271-2
  • Type

    conf

  • DOI
    10.1109/VDAT.2010.5496712
  • Filename
    5496712