An 8.2 to 20.1 GHz LC PLL with Sub-100 fs Jitter in 0.13 µm SiGe BICMOS

A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fs_rms when N=2 and 206.1 fs_rms when N=16. In addition, the PLL achieves loop bandwidths up to 100 MHz which enables it to be used as a clean-up PLL at the receiver. In order to provide low jitter and low reference spurs for a wide range of reference frequencies, a novel architecture that uses switched multi-pole spur-reduction filters with dedicated phase detectors is introduced. The spur levels at the output are -55 dBc and -62 dBc when N=2 and N=16, respectively. Implemented in a 0.13 μm SiGe BiCMOS process, the 1.31 mm2 PLL dissipates a total of 302 mW from 1.2 V and 2.5 V supplies.