Algorithm and architecture design for the implementation of high order FIR filters using the residue number system

The computational speed requirements of future signal processing algorithms necessitate the use of special purpose multiprocessor systems implemented using VLSI technology. Finite field arithmetic and algorithms offer an extra degree of freedom in the design of high performance integrated circuits and, motivated by the need for high order and high performance FIR digital filters, the paper investigates some issues in maximising the benefits obtained from the residue number system (RNS) of arithmetic whilst maintaining the ability to use sophisticated finite field algorithms for a VLSI implementation. RNS arithmetic and tailored finite filed algorithms have been used to design an architecture for the implementation of high order, high performance FIR digital filters. Specifically a number of relatively small moduli are used to implement long FIR filters via an algorithm derived from the Agarwal-Cooley algorithm. Cyclic convolutions are, where possible, implemented via number theoretic transforms in the respective moduli with prime factor algorithms used to reduce the computational expense. A key improvement of the algorithm implementation is the elimination of explicit on chip data reordering. The resulting systolic structure is well suited to VLSI implementation and a demonstration system has been constructed to prove the validity of the ideas