DocumentCode :
2820263
Title :
Dangling-wire avoidance routing for crossbar switch structured ASIC design style
Author :
Hung, Yi-Huang ; Li, Hung-Yi ; Hsu, Po-Yang ; Liu, Yi-Yu
Author_Institution :
Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan
fYear :
2010
fDate :
26-29 April 2010
Firstpage :
177
Lastpage :
180
Abstract :
In the routing architecture of a structured ASIC, crossbar is one of the most area efficient switch blocks. Nevertheless, dangling-wire occurs when there is a routing bend in crossbar switch. The dangling-wire incurs longer wire length as well as higher interconnection capacitance. In this paper, we are motivated to tackle dangling-wire routing issues for structured ASIC. We first propose a compact graph model for crossbar switch routing. With our graph model, switch connectivity relations can be removed to keep the 2-D structured ASIC routing graph efficient and to speed up run-time of our routing algorithm. Furthermore, we leverage state-of-the-art techniques into our routing framework, which contains deferred pin assignment, Steiner point re-assignment, and anchor pair insertion, to minimize dangling-wires taking both total wire length and routing congestion into account. The experimental results demonstrate that our proposed routing framework greatly reduces 21% dangling-wires, 34% channel width, and 13% total wire length as compared with VPR using crossbar switch.
Keywords :
application specific integrated circuits; capacitance; integrated circuit design; integrated circuit interconnections; network routing; 2D structured ASIC routing graph; Steiner point reassignment; anchor pair insertion; area efficient switch blocks; channel width; compact graph model; crossbar switch structured ASIC design; dangling-wire avoidance routing; deferred pin assignment; interconnection capacitance; routing algorithm; routing architecture; routing congestion; total wire length; Application specific integrated circuits; Capacitance; Costs; Design engineering; Fabrication; Field programmable gate arrays; Logic design; Routing; Switches; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
Type :
conf
DOI :
10.1109/VDAT.2010.5496719
Filename :
5496719
Link To Document :
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