Title :
An optimal latching waveform design for dynamic sense amplifiers
Author :
Yuan, Jiann S. ; Liou, Juin J.
Author_Institution :
Dept. of Electr. Eng., Univ. of Central Florida, Orlando, FL, USA
Abstract :
A generalized optimal latching pulse for DRAM dynamic sense amplifier design has been derived. The model equations account for threshold voltage (Vt) imbalance, bit line capacitance (Cb) imbalance, current gain (β) imbalance, gate capacitance (CG) and intrabit line capacitive (CI) coupling effect, channel length modulation, source-body effect, and temperature sensitivity in a unified manner. Computer simulations of the analytical equations, including those effects, are presented. A design implementation for fast sense amplifier operation is also presented to demonstrate the utility of the model equations for practical application
Keywords :
DRAM chips; MOS integrated circuits; DRAM; analytical equations; bit line capacitance; bit line capacitance imbalance current gain imbalance; channel length modulation; design implementation; dynamic sense amplifiers; fast sense amplifier operation; gate capacitance coupling effect; intrabit line capacitive coupling effect; model; model equations; optimal latching pulse; optimal latching waveform design; source-body effect; temperature sensitivity; threshold voltage imbalance; Application software; Capacitance; Computer simulation; Equations; Operational amplifiers; Power dissipation; Pulse amplifiers; Random access memory; Temperature sensors; Threshold voltage;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140872
