DocumentCode
2820580
Title
A 35.56GHz all-digital phase-locked loop with high resolution varactors
Author
Hung, Chao-Ching ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2010
fDate
26-29 April 2010
Firstpage
245
Lastpage
248
Abstract
A 35.56GHz all-digital phase-locked loop with high resolution varactors is presented. To enhance the frequency resolution for a high-frequency digitally controlled oscillator, the proposed varactor with its body connected to digital control bits is presented. A 35.56GHz all-digital PLL is realized in 90nm CMOS process. The measured peak-to-peak jitter and rms jitter are 3.84ps and 349.1fs, respectively, at 35.56GHz.
Keywords
CMOS digital integrated circuits; MMIC oscillators; field effect MMIC; phase locked loops; varactors; CMOS process; all digital phase locked loop; frequency 35.56 GHz; high frequency digitally controlled oscillator; high resolution varactor; size 90 nm; Capacitance; Capacitors; Digital control; Frequency; Jitter; MOS devices; Performance gain; Phase detection; Phase locked loops; Varactors; all-digital; high frequency resolution; phase-locked loop; varactor;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location
Hsin Chu
Print_ISBN
978-1-4244-5269-9
Electronic_ISBN
978-1-4244-5271-2
Type
conf
DOI
10.1109/VDAT.2010.5496735
Filename
5496735
Link To Document