Title :
Optimum leakage dynamic array design
Author :
Bajkowski, Maciej ; Pham, Giao ; Vepadharmalingam, Murali
Abstract :
In recent microprocessor designs Register File (RF) and Read Only Memory (ROM) arrays comprise over 50% of the total core area. These arrays account for a significant portion of the total leakage power. We propose two novel design techniques: Tri-state Domino Circuit (TDC) and Selective Pre-Charge (SPC). We combine these techniques to maximize leakage savings without affecting downstream logic by using a new noise robust state preserving Set Dominant Latch (SDL). Our simulation results, in 32nm CMOS technology, demonstrate that we are able to reduce the read path leakage power for a 256 entry 1 rlw RF by 81%.
Keywords :
CMOS logic circuits; flip-flops; logic circuits; logic design; microprocessor chips; shift registers; CMOS technology; downstream logic; microprocessor designs register file; optimum leakage dynamic array design; read only memory arrays; selective pre-charge; set dominant latch; size 32 nm; tri-state domino circuit; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Latches; Microprocessors; Noise robustness; Radio frequency; Read only memory; Registers;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496739
