Title :
Delay-modeling of NAND gates
Author :
Vemuru, Srinivasa R ; Thorbjornsen, Arthur R.
Author_Institution :
Dept. of Electr. Eng., Toledo Univ., OH, USA
Abstract :
A model for evaluating the propagation delay, rise and fall time of NAND gates is proposed. The model includes the shape of the input waveform, the capacitive load, and the transconductances of the NMOS and the PMOS transistors. The effect of the position of the first active input is included in the model. The proposed model is compared with SPICE for accuracy and computation speed
Keywords :
CMOS integrated circuits; NAND circuits; circuit analysis computing; integrated logic circuits; logic gates; NAND gates; SPICE; capacitive load; computation speed; delay modeling; fall time; propagation delay; transconductances; CMOS logic circuits; Circuit simulation; Computational modeling; Inverters; Logic gates; MOS devices; MOSFETs; Propagation delay; SPICE; Voltage;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140873
