A low-area and short-time scan-based embedded delay measurement using signature registers

This paper presents a low-area and short-time scan design for delay measurement using signature registers. The number of redundant latches is reduced utilizing X bits of test data for the delay measurement. After that, with the optimization of the scan chain routing, the scan chain length is reduced without decrease of the number of the measurable paths. These techniques keep the area overhead in the same order of that of the conventional scan designs for testing. In addition, the techniques further reduce the measurement time. Evaluation shows that the area overhead is 22.1% larger and 24.0% smaller than standard scan design and enhanced scan design respectively, which is in the order of scan designs for test. The measurement time is 90% shorter than that of standard scan design.