Analysis of the switching characteristics of NMOS common drain FET logic (CDFL)

Author

Maa, Yann Jiun ; Abdel-motaleb, Ibrahim M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA

fYear

1990

fDate

12-14 Aug 1990

Firstpage

926

Abstract

The switching characteristics of a novel NMOS structure, the common drain FET logic (CDFL) is studied. A technique utilizing a load capacitor charging and discharging mechanism to calculate the output waveform of NMOS CDFL buffer and DCFL (direct coupled FET logic) inverter has been used. The results show that a CDFL buffer can be at least twice as fast as a DCFL inverter occupying the same area. Using the buffer to build positive logic gates and the inverter to build negative logic gates leads to at least at 100% increase in the speed of the overall circuit and a 33% decrease in the occupied area

Keywords

MOS integrated circuits; integrated logic circuits; logic gates; switched networks; CDFL; CDFL buffer; DCFL; DCFL inverter; NMOS structure; chip area reduction; common drain FET logic; direct coupled FET logic; load capacitor charging; negative logic gates; output waveform; positive logic gates; speed increase; switching characteristics; Capacitance; FETs; Gallium arsenide; Logic circuits; Logic gates; MOS devices; Pulse inverters; Switched capacitor circuits; Voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Conference_Location

Calgary, Alta.

Print_ISBN

0-7803-0081-5

Type

conf

DOI

10.1109/MWSCAS.1990.140874

Filename

140874