A 24 dB gain 51–68 GHz CMOS low noise amplifier using asymmetric-layout transistors

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (D_gd) has been enlarged to obtain a better maximum available gain (MAG). A 0.6 dB MAG improvement is realized when D_gd changes from 60 nm to 200 nm. By using the asymmetric-layout transistor, a four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.