A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Following the circuit integration trend, the process monitoring structures need to predict the production circuits reliability while keeping test time small and preserving the wafer area. The design presented monitors a 40nm CMOS bitcell failure evolution with supply voltage within a 260kb SRAM matrix and reports the number of fails through an integer-to-current converter. It approximates huge population bitcells reliability while reusing scribe lane test equipment. The design test time is 1s per voltage value; the design height is limited to 60um to fit in sawing region between circuits.