DocumentCode :
2821226
Title :
Arithmetic structures for AES cryptographic systems
Author :
Abd-El-Barr, Mostafa ; Al-Noori, Aisha
Author_Institution :
Department of Information Science, College of Computing Sciences and Engineering, Kuwait University
fYear :
2015
fDate :
26-27 Feb. 2015
Firstpage :
1367
Lastpage :
1373
Abstract :
The Advanced Encryption Standard (AES) is a symmetric key block cipher cryptosystem adopted by the NIST as the world standard for data encryption/decryption. Multi-valued logic (MVL), as opposed to two-valued logic (TVL), is a propositional calculus in which there are more than two truth values. Multiple-valued logic offers opportunities for overcoming a number of difficulties facing TVL such as chip area, power consumption, and delay. A number of researchers have conducted intensive research work in attempts to improve and enhance the performance of cryptographic systems in terms of speed, area, and power consumption. In this paper, we present a number of arithmetic operations required by the AES cryptosystem using both TVL and MVL. We also cover the Galois field arithmetic operations performed in cryptographic systems.
Keywords :
Digital signal processing; Encryption; Galois fields; Multiplexing; Power demand; Standards; AES Cryptosystem; Cryptography; Galois field arithmetic; MVL Arithmetic Operations; Multi-valued logic (MVL);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics and Communication Systems (ICECS), 2015 2nd International Conference on
Conference_Location :
Coimbatore, India
Print_ISBN :
978-1-4799-7224-1
Type :
conf
DOI :
10.1109/ECS.2015.7124808
Filename :
7124808
Link To Document :
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