Generation of the three stages NAND gate circuits with the single rail inputs by using the inhibiting loop method

A new method is presented for minimizing a three-stage NAND gate circuit having single-rail inputs, in terms of both the number of gates. Such a circuit is realized by using the inhibiting loop method in the circuit synthesis on the Karnaugh map. Both the inhibiting loops and the inhibited loops are chosen in such a way that they will occupy the maximum area within the cell area including the permissible loops and the other 1-cells or 0-cells. In addition, a negative literal loop is adopted. The minimal covering is made from the several prime permissible terms chosen. This method was applied to generation of the circuits for the 51 three-variable P-equivalence classes and the 68 four-variable functions by running the COMMON LIPS language programs on the computer, microVAX-II. Then the results of generation were compared with the ideal minimized results obtained by manual calculation. Better agreement was found