A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR

A digital calibration scheme is proposed to reduce the power consumption in a switched-capacitor (SC) ΔΣ ADC. When opamp bias current is reduced in the integrators, nonlinear settling errors dominate the output spectrum, causing harmonic distortion. The errors are detected using a parallel structure, and their effect is reduced by passing the post-filtered digital output through an inverse nonlinearity. With calibration, experimental results over a signal bandwidth of 1 MHz yield a peak signal-to-noise-and-distortion ratio (SNDR) of 75 dB, a total harmonic distortion (THD) of -90 dB and a spurious-free dynamic range (SFDR) of 94 dB. The power dissipation of the calibrated modulator is 5 mW, a savings of 38% over a similarly performing uncalibrated ADC. The active area is 0.39 mm² in 0.25-μm CMOS.