Title :
A thermal van der Pauw test structure
Author :
Paul, O. ; Plattner, L. ; Baltes, H.
Author_Institution :
Inst. for Microsyst. Technol., Freiburg Univ., Germany
Abstract :
A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The analogy between the two-dimensional heat flow in thin film samples and the electrical current pattern in thin film conductors is exploited. A thermal sheet resistance of 1.87×105 K/W was extracted from the complete sandwich of dielectric layers of a commercial CMOS ASIC process. This is equivalent to an average in-plane thermal conductivity of the CMOS dielectric layer sandwich of κ=1.44 Wm-1 K -1
Keywords :
CMOS integrated circuits; application specific integrated circuits; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; micromachining; thermal analysis; thermal conductivity measurement; thermal resistance; 2D heat flow; CMOS ASIC process; CMOS dielectric layer sandwich; SiO2-Si; dielectric layers; electrical current pattern; electrical van der Pauw Greek cross test structures; in-plane thermal conductivity; in-plane thermal sheet conductivity; micromachined thermal van der Pauw test structure; thermal sheet resistance; thermal van der Pauw test structure; thin film conductors; thin film samples; Conducting materials; Contacts; Current density; Density estimation robust algorithm; Dielectric thin films; Heating; Resistors; Slabs; Testing; Thermal conductivity;
Conference_Titel :
Microelectronic Test Structures, 1999. ICMTS 1999. Proceedings of the 1999 International Conference on
Conference_Location :
Goteborg
Print_ISBN :
0-7803-5270-X
DOI :
10.1109/ICMTS.1999.766216
