A statistical noise-tolerance analysis and test structure for logic families

Technology downscaling and high performance architectures are the main trends in high speed CMOS VLSI circuits. These two factors require respectively increasing device integration and the design of new dynamic logic families for high level pipelining structures. An increasingly pressing problem connected to this trend is crosstalk noise between interconnections and self-induced noise due to simultaneous switching of large numbers of gates. A test IC was realized for noise tolerance measurement of high speed CMOS logic families. Variable energy noise events are internally generated using integrated inductors that switch according to a programmable combination of control signals. The effects of the injected noise are measured in terms of logic errors by a detection structure: a statistic for the measured outputs is created and compared with the results of a simulation tool for the evaluation of noise tolerance in CMOS logic families