Test structure design for a fast and simple evaluation of carrier mobilities in highly injected regions

Author

Persiano, G.V.

Author_Institution

Facolta di Ingegneria, Univ. del Sannio, Benevento, Italy

fYear

1999

fDate

1999

Firstpage

99

Lastpage

104

Abstract

This paper describes the use and the design of a microelectronic test structure to show a new fast and simple DC method for measuring the dependence of carrier mobilities upon carrier concentration. The test structure is designed for reducing parasitic effects and providing reliable results up to the highest carrier concentrations. Numerical simulation is used for verification of the accuracy of the method for several test structure parameters. Experimental results are provided and represented by a simple fitting formula

Keywords

carrier density; carrier mobility; curve fitting; integrated circuit design; integrated circuit modelling; integrated circuit testing; numerical analysis; DC measurement method; IC test structure design; carrier concentration; carrier mobility; fitting formula; highly injected regions; microelectronic test structure; microelectronic test structure design; numerical simulation; parasitic effects; test structure parameters; Charge carrier processes; Current density; Diodes; Doping; Fitting; Microelectronics; Numerical simulation; Scattering; Substrates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1999. ICMTS 1999. Proceedings of the 1999 International Conference on

Conference_Location

Goteborg

Print_ISBN

0-7803-5270-X

Type

conf

DOI

10.1109/ICMTS.1999.766224

Filename

766224