Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics

Author

Ghibaudo, Gerard ; Bruyere, S. ; Devoivre, T. ; DeSalvo, B. ; Vincent, E.

Author_Institution

Lab. de Phys. des Composants a Semicond., ENSERG, Grenoble, France

fYear

1999

fDate

1999

Firstpage

111

Lastpage

116

Abstract

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian´s technique (Maserjian et al., Solid State Electron. vol. 17, pp. 335-9, 1974) and of Vincent´s method (Vincent et al., Proc. IEEE Microelectronic Test Structures vol. 10, pp. 105-10, 1997) is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm down to 1.8 nm

Keywords

CMOS integrated circuits; MIS structures; dielectric thin films; integrated circuit measurement; thickness measurement; 1.8 to 7 nm; CMOS technology; MOS structures; Maserjian´s technique; SiO₂-Si; Vincent´s method; carrier statistics; extraction procedures; gate oxide thickness; oxide thickness; oxide thickness extraction; ultra-thin gate dielectrics; CMOS technology; Capacitance measurement; Data mining; Dielectrics; Extrapolation; Linear predictive coding; Microelectronics; Statistical distributions; Statistics; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1999. ICMTS 1999. Proceedings of the 1999 International Conference on

Conference_Location

Goteborg

Print_ISBN

0-7803-5270-X

Type

conf

DOI

10.1109/ICMTS.1999.766226

Filename

766226