Architecture design and VLSI implementation for JPEG2000

This paper presents an architecture design for JPEG2000 with a fast algorithm in EBCOT. The EBCOT algorithm takes advantages of resolution and SNR scalability together with a random access property, but its complexity also becomes the bottleneck of JPEG2000. In this paper, the authors proposed an architecture by using two speed-up methods. The two speed-up methods can reduce the 43% clock cycles for EBCOT context modeling. This architecture works in 40 MHz. The area of JPEG2000 is about 79787 gate counts.