Title :
High throughput rate EBCOT architecture for JPEG2000
Author :
Chiang, Jen-Shiun ; Chang, Chun-Hau ; Lin, Yu-Sen ; Hsieh, Chang-Yuo
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
Abstract :
This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The Tier-1 of the EBCOT consumes most of the time in a JPEG2000 encoding system. The proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, an efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. To compare to the conventional context-modeling architecture the presented parallel architecture can improve the throughput rate up to 25%. Because of the high throughput rate of the parallel context-modeling architecture, the concept of multi-rate processing for low power design can be applied.
Keywords :
block codes; codecs; image coding; integrated circuit design; parallel architectures; 185 MHz; EBCOT architecture; JPEG2000; embedded block coding; matching arithmetic coder; parallel context modeling coding architecture; throughput rate; Arithmetic; Block codes; Context modeling; IEC standards; ISO standards; Image coding; Parallel architectures; Rate-distortion; Throughput; Transform coding;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562360