Title :
Test structure for direct extraction of capacitance matrix in VLSI
Author :
Mido, T. ; Ito, H. ; Asada, K.
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each component is directly obtained from the measurement data without any calculation as the difference between current values for driver unit and reference unit, and the total pads are kept at 8 independently of the size of target matrix. As a result of evaluation of measurement errors due to the asymmetry of the structures, this new method can measure components of capacitance matrix with femto-farad order precision
Keywords :
VLSI; capacitance; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; measurement errors; VLSI; capacitance matrix; direct capacitance matrix extraction; driver unit-reference unit current difference; measurement data; measurement errors; multilayer interconnections; target matrix size; test structure; test structure asymmetry; Capacitance measurement; Circuit testing; Conductors; Current measurement; Data mining; Delay estimation; Driver circuits; Integrated circuit interconnections; Parasitic capacitance; Very large scale integration;
Conference_Titel :
Microelectronic Test Structures, 1999. ICMTS 1999. Proceedings of the 1999 International Conference on
Conference_Location :
Goteborg
Print_ISBN :
0-7803-5270-X
DOI :
10.1109/ICMTS.1999.766243
