A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications

Author

van den Bosch, A. ; Steyaert, M. ; Sansen, W.

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

fYear

1999

fDate

1999

Firstpage

212

Lastpage

215

Abstract

In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance due to the small area. The matching properties of this structure have been investigated and these results have been compared to those for traditional finger style structures. Exploiting these advantages, these transistors are very well suited for high speed applications with a demand for both good matching and small area, such as e.g. multi-bit current steering D/A converters. The test chips have been implemented in a standard 0.5 μm CMOS technology. No adaptations to the technology have been made in order to realize the structures

Keywords

CMOS integrated circuits; MOSFET; capacitance; digital-analogue conversion; high-speed integrated circuits; integrated circuit design; integrated circuit testing; 0.5 micron; CMOS hexagonal transistor structure; CMOS technology; finger style structures; high density matched hexagonal transistor structure; high speed applications; matched hexagonal transistor structure; multi-bit current steering D/A converters; parasitic drain capacitance; parasitic source capacitance; standard CMOS technology; structure matching properties; test chips; CMOS technology; Circuit synthesis; Circuit testing; Fingers; MOSFETs; Parasitic capacitance; Uniform resource locators; Voltage; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1999. ICMTS 1999. Proceedings of the 1999 International Conference on

Conference_Location

Goteborg

Print_ISBN

0-7803-5270-X

Type

conf

DOI

10.1109/ICMTS.1999.766245

Filename

766245