Title :
An adaptive partitioning scheme for DRAM-based cache in Solid State Drives
Author :
Hyotaek Shim ; Bon-Keun Seo ; Jin-Soo Kim ; Maeng, Seungryoul
Author_Institution :
Comput. Sci. Dept., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Abstract :
Recently, NAND flash-based Solid State Drives (SSDs) have been rapidly adopted in laptops, desktops, and server storage systems because their performance is superior to that of traditional magnetic disks. However, NAND flash memory has some limitations such as out-of-place updates, bulk erase operations, and a limited number of write operations. To alleviate these unfavorable characteristics, various techniques for improving internal software and hardware components have been devised. In particular, the internal device cache of SSDs has a significant impact on the performance. The device cache is used for two main purposes: to absorb frequent read/write requests and to store logical-to-physical address mapping information. In the device cache, we observed that the optimal ratio of the data buffering and the address mapping space changes according to workload characteristics. To achieve optimal performance in SSDs, the device cache should be appropriately partitioned between the two main purposes. In this paper, we propose an adaptive partitioning scheme, which is based on a ghost caching mechanism, to adaptively tune the ratio of the buffering and the mapping space in the device cache according to the workload characteristics. The simulation results demonstrate that the performance of the proposed scheme approximates the best performance.
Keywords :
DRAM chips; cache storage; disc drives; flash memories; storage allocation; DRAM-based Cache; NAND flash memory; adaptive partitioning; buffering space; internal device cache; logical-to-physical address mapping information; mapping space; read-write request; solid state drive; Computer buffers; Computer science; Drives; Partitioning algorithms; Portable computers; Random access memory; SDRAM; Solid state circuits; Space technology; Throughput;
Conference_Titel :
Mass Storage Systems and Technologies (MSST), 2010 IEEE 26th Symposium on
Conference_Location :
Incline Village, NV
Print_ISBN :
978-1-4244-7152-2
Electronic_ISBN :
978-1-4244-7153-9
DOI :
10.1109/MSST.2010.5496995