FPGA design for image processing using a GUI of a web-based VHDL Code Generator

The aim of our web-based VHDL Code Generator, named DiaHDL, is, to translate a component diagram to synthesizable VHDL code [1][2]. In this live demonstration we present the special Graphical User Interface (GUI) of this web- based tool that allows the user to select digital components, customize their parameters und generate the VHDL code. This is done for an FPGA design for image processing, a JPEG encoder. We show the complete design flow from component entry to bit stream generation for programming a Xilinx FPGA device, using the proposed GUI of DiaHDL tool together with Xilinx ISE tool, a standard HDL synthesis tool.