Fast acquisition techniques for low-speed digitally implemented demodulators

In order to test various ideas concerning digitally implemented demodulators and fast acquisition techniques for satellite communications the author designed a digital signal processor (DSP) based on three TMS320C25 devices. Computer simulations of the various components of a digitally implemented demodulator are a powerful tool but they can also be very slow. The specialised DSP hardware can demodulate QPSK signals at rates of up to 128 kbit/s and can prove various strategies in real-time in a true environment. The flexibility of the software approach allows many characteristics to be altered rapidly, the techniques developed on this test bed can then be implemented in hardware for much higher speed operation