DocumentCode :
2822106
Title :
Power minimization for clustered routing in network on chip architectures
Author :
Blessington, T. Praveen ; Murthy, B. Bhanu ; Basha, Fazal Noor
Author_Institution :
ECE Dept., KL Univ., Vaddeswaram, India
fYear :
2015
fDate :
26-27 Feb. 2015
Firstpage :
1584
Lastpage :
1588
Abstract :
Traditional System-on-Chip (SoC) design employs shared buses for data transfer among various subsystems. As SoC becomes more complex involving a larger number of subsystems, traditional bus-based architecture is giving way to a new paradigm for on-chip communication. A communication network of point-to-point links and routing switches is used to facilitate communication between the subsystems. The considerations that have driven data communication from shared buses to packet-switching networks in clustered architectures (spatial reuse, multi-hop routing, flow and congestion control, and standard interfaces for design reuse, etc.) will inevitably drive VLSI designers to use these principles in on-chip interconnects.
Keywords :
VLSI; integrated circuit interconnections; network routing; network-on-chip; packet switching; pattern clustering; SoC; VLSI; bus-based architecture; clustered routing; data transfer; network on chip architecture; on-chip communication; on-chip interconnect; packet-switching network; point-to-point link; power minimization; routing switch; system-on-chip; very large scale integration; Computer architecture; Engines; Network-on-chip; Routing; Routing protocols; Very large scale integration; Architectures; Average packet-latency; Mesh; NOC; Router; Xpipes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics and Communication Systems (ICECS), 2015 2nd International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-7224-1
Type :
conf
DOI :
10.1109/ECS.2015.7124854
Filename :
7124854
Link To Document :
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