DocumentCode
2822205
Title
Selective guarded execution using profiling on a dynamically scheduled processor
Author
Mantripragada, Srinivas ; Nicolau, Alexandru
Author_Institution
Silicon Graphics Inc., Mountain View, CA, USA
fYear
2000
fDate
36861
Firstpage
15
Lastpage
22
Abstract
Modern dynamically scheduled processors use branch prediction hardware to speculatively fetch and execute most likely executed paths in a program. Complex branch predictors have been proposed which attempt to identify these paths accurately such that the hardware can benefit from out-of-order (OOO) execution. Recent studies have shown that inspite of such complex prediction schemes, there still exist many frequently executed branches which are difficult to predict. Predicated execution has been proposed as an alternative technique to eliminate some of these branches in various forms ranging from a restrictive support to a full-blown support. We call the restrictive form of predicated execution as guarded execution. In this paper, we propose a new algorithm which uses profiling and selectively performs if-conversion for architectures with guarded execution support. Branch profiling is used to gather the taken, non-taken and misprediction counts for every branch. This combined with block profiling is used to select paths which suffer from heavy mispredictions and are profitable to if-convert. Effects of three different selection criterias, namely size-based, predictability-based and profiled-based on net cycle improvements, branch mispredictions and mis-speculated instructions are then studied. We also explain numerous adjustments that were made to the selection criterias to better reflect the OOO processor behaviour
Keywords
parallel architectures; processor scheduling; branch prediction; dynamically scheduled processor; frequently executed branches; guarded execution support; if-conversion; out-of-order; prediction schemes; profiling; Accuracy; Computer science; Dynamic scheduling; Graphics; Hardware; Out of order; Parallel processing; Pipelines; Processor scheduling; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1999. International Workshop
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-7695-0650-x
Type
conf
DOI
10.1109/IWIA.1999.898839
Filename
898839
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