DocumentCode :
2822214
Title :
Near fine grain parallel processing using static scheduling on single chip multiprocessors
Author :
Kimura, Keiji ; Kasahara, Hironori
Author_Institution :
Dept. of Electr., Electron. & Comput. Eng., Waseda Univ., Tokyo, Japan
fYear :
2000
fDate :
36861
Firstpage :
23
Lastpage :
31
Abstract :
With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting important problems However, it has been thought that popular superscalar and VLIW world have difficult to obtain scalable improvement of effective performance in future because of the limitation of instruction level parallelism. To cope with this problem, a single chip multiprocessor (SCM) approach with multi grain parallel processing inside a chip, which hierarchically exploits loop parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism, is thought one of the most promising approaches. This paper evaluates effectiveness of the single chip multiprocessor architectures with a shared cache, global registers, distributed shared memory and/or local memory for near fine grain parallel processing as the first step of research on SCM architecture to support multi grain parallel processing. The evaluation shows OSCAR (Optimally Scheduled Advanced Multiprocessor) architecture having distributed shared memory and local memory in addition to centralized shared memory and attachment of global register gives us significant speed rip such as 13.8% to 143.8% for four processors compared with shared cache architecture for applications which have been difficult to extract parallelism effectively
Keywords :
distributed shared memory systems; microprocessor chips; multiprocessing systems; parallel architectures; performance evaluation; OSCAR; SCM; coarse grain parallelism; distributed shared memory; fine grain parallel processing; global registers; loop parallelism; multi grain parallel processing; near fine grain parallel processing; shared cache; shared cache architecture; single chip multiprocessor; single chip multiprocessors; static scheduling; Algorithms; Computer architecture; Costs; Microprocessors; Parallel processing; Processor scheduling; Registers; Uniform resource locators; VLIW; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1999. International Workshop
Conference_Location :
Maui, HI
ISSN :
1537-3223
Print_ISBN :
0-7695-0650-x
Type :
conf
DOI :
10.1109/IWIA.1999.898840
Filename :
898840
Link To Document :
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