Title :
Evaluation of compiler-assisted software DSM schemes for a workstation cluster
Author :
Niwa, Junpei ; Inagaki, Tatsushi ; Matsumoto, Takashi ; Hiraki, Kei
Author_Institution :
Dept. of Inf. Sci., Tokyo Univ., Japan
Abstract :
To execute shared-memory parallel programs efficiently on distributed-memory systems without remote-caching hardware mechanisms, software-caching mechanisms must be used. We have proposed two compiler-assisted software-caching schemes. One is a page-based system (Asymmetric Distributed Shared Memory: ADSM) that uses virtual memory mechanisms only for read cache-misses. The other is a full user-level system (User-level Distributed Shared Memory: UDSM) that uses user-level checking codes and consistency-management codes. In these schemes, art optimizing compiler directly analyses the shared-memory source programs and optimizes them. It exploits the capabilities of middle-grained or coarse-grained remote-memory accesses to reduce the volume of communications and to reduce the overhead of the cache-emulation codes. It performs interprocedural points-to analysis, interprocedural shared-access set calculations by using interval analysis to solve redundancy elimination equations along with lazy release consistency model. We implemented this optimizing compiler for both ADSM and UDSM, and run-time system for user-level cache-emulation. The run-time system runs on an SS20 workstation cluster connected with a 100BASE-TX Ethernet. Both schemes achieve a high speed-rip ratio with the SPLASH-2 benchmark suite. The experimental results show that the combination of the optimizing compiler and Software DSM is very effective. The experimental results also show that the performance of the ADSM scheme is limited by the communication of unnecessary data, while that of the UDSM scheme is limited by the instrumentation overhead
Keywords :
cache storage; distributed shared memory systems; optimising compilers; workstation clusters; ADSM; Asymmetric Distributed Shared Memory; DSM; compiler-assisted; distributed-memory systems; optimizing compiler; software-caching; user-level system; virtual memory mechanisms; workstation cluster; Computer networks; Distributed computing; Hardware; Information science; Instruments; Optimizing compilers; Performance analysis; Program processors; Support vector machines; Workstations;
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1999. International Workshop
Conference_Location :
Maui, HI
Print_ISBN :
0-7695-0650-x
DOI :
10.1109/IWIA.1999.898843