Using module-level Evolvable Hardware approach in design of sequential logic circuits

In this study, we propose a module-level Evolvable Hardware (EHW) approach to design synchronous sequential circuits and minimize the circuit complexity (the number of logic gates and wires used). Firstly, we use Genetic Algorithm (GA) to implement state simplification and obtain near-optimal state assignment. Then, in the pre-evolution stage, EHW evolves a set of high performing circuits and uses data mining method to find frequently evolved blocks from these circuits. The frequently evolved block would be re-used as function or terminal for evolving better circuits in the re-evolution stage. EHW has a faster convergence so that the circuit with small complexity could be evolved. Auto starting ability of circuits would also be test by the fitness function of EHW. Finally, sequence detectors, modulon counters, and ISCAS´89 circuit are used as the proof for our evolutionary design approach. Simulation results are given, and our evolutionary algorithm is shown to be better than other methods in terms of convergence time, success rate, and maximum fitness across generations.