DocumentCode
2822344
Title
Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs
Author
Young, Ian A.
Author_Institution
Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA
fYear
2010
fDate
14-16 Sept. 2010
Firstpage
61
Lastpage
70
Abstract
Scaling of CMOS technology has made major innovations in the last decade with the introduction of strained silicon and high-k metal gate, however at the same time an increasing amount of complex analog mixed-signal circuit functionality has been integrated on microprocessors and SOCs. Examples of the key analog mixed-signal circuit functional blocks implemented in advanced 45nm and 32nm logic CMOS on microprocessors and SOCs are described. Techniques that overcome the challenges of the low supply voltage and dimensional scaling in 45 nm and 32nm CMOS include the use of the digital transistor for analog circuits, the use of “digital assist” logic for calibration and differential pair offset cancellation. The co-optimization of design techniques and process enhancements for high performance RF wireless circuits integrated on SOCs was employed to manage complexity and cost.
Keywords
CMOS logic circuits; circuit optimisation; low-power electronics; microprocessor chips; mixed analogue-digital integrated circuits; nanoelectronics; radiofrequency integrated circuits; system-on-chip; transistor circuits; RF wireless circuit; SoC; advanced nano-scale CMOS technology; analog mixed-signal circuit; calibration; cooptimization; differential pair offset cancellation; digital assist logic; digital transistor; dimensional scaling; logic CMOS; low supply voltage; microprocessor; size 32 nm; size 45 nm; Analog circuits; CMOS integrated circuits; Clocks; Logic gates; Metals; Microprocessors; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC, 2010 Proceedings of the
Conference_Location
Seville
ISSN
1930-8833
Print_ISBN
978-1-4244-6662-7
Type
conf
DOI
10.1109/ESSCIRC.2010.5619780
Filename
5619780
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