Simulation of acquisition in phase-locked loops incorporating phase-frequency detectors

The time required for a phase-locked loop (PLL) to acquire lock is an important design parameter. Most modern PLLs incorporate a phase-frequency detector because out of lock it behaves as a frequency discriminator and aids acquisition. However, a correct analysis of the acquisition behavior of this type of loop has yet to be presented, mainly because of confusion regarding the pulse output duty cycle of the phase detector. The first correct analysis of the acquisition behavior is presented. The result is confirmed by simulation. Data are presented for both second- and third-order loops