DocumentCode
2822592
Title
Efficient systolic array for singular value and eigenvalue decomposition
Author
Ahmedsaid, A. ; Amira, A. ; Bouridane, A.
Author_Institution
Sch. of Comput. Sci., The Queen´´s Univ., Belfast, UK
Volume
2
fYear
2003
fDate
27-30 Dec. 2003
Firstpage
835
Abstract
This paper presents an efficient systolic array for the computation of the singular value decomposition (SVD) and the symmetric eigenvalue decomposition (EVD). The proposed architecture is three times more efficient and faster than the Brent, Luk, Van Loan (BLV) SVD/EVD systolic array. The architecture has been implemented efficiently on FPGA using a high level language for hardware design "Handel-C".
Keywords
digital arithmetic; eigenvalues and eigenfunctions; field programmable gate arrays; hardware description languages; singular value decomposition; systolic arrays; FPGA; Handel-C; eigenvalue decomposition; hardware design; high level language; singular value decomposition; systolic array; Computer architecture; Eigenvalues and eigenfunctions; Field programmable gate arrays; Hardware; Image analysis; Jacobian matrices; Matrix decomposition; Principal component analysis; Singular value decomposition; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562416
Filename
1562416
Link To Document