A high performance Optical Network on Chip based on Clos topology

Traditional metallic interconnects has become the bottleneck of NoC (Network on Chip) performance due to the limited bandwidth, long delay, high power consumption and crosstalk noise. Optical Network-on-Chip (ONoC) can decrease interconnect delays and provide higher bandwidth, lower power consumption. So ONoC is believed to be a promising solution. ONoC is based on silicon-based waveguides and CMOS-compatible microresonators. This paper proposes a 64-core Clos-based ONOC (CNoC) including its topology, floorplan and routing strategy and two optimized optical routers. CNoC is built from a strictly non-blocking network, Clos (15, 8, 8). It carries payload packets in an optical network while control packets in a separate electronic network. Two optical routers and a distributed routing algorithm are developed for CNoC application. Through a simulator Opnet, we compare the 64-core CNoC with mesh-based optical NoC and another Clos (8, 8, 8)-based OnoC. ETE delay and network throughput are analyzed under different offered loads and various packet sizes.